1. Field of the Invention
This invention relates generally to semiconductor-based programmable memory arrays and more particularly to an improved fuse structural layout to provide increased array density.
2. Description of Prior Art
In the prior art, fuse programmable arrays of the type including rows and columns of semiconductor cells, such as could be used for Programmable Logic Devices (PLDs) or Programmable Read Only Memories (PROMs), were laid out rather conservatively in terms of semiconductor wafer space to provide easily programmable cells by ensuring that there was adequate spacing around fuses to permit easy severing of those fuses. This arises because of the typical 6 micron laser spot size and due to the typical 1-2 micron positioning tolerance available with commercially available laser systems. FIG. 1 is a top plan view of a portion of a typical prior art fuse programmable array 1. This structure is illustrated in commonly owned U.S. patent application Ser. No. 07/051,971, filed May 19, 1987, entitled "Laser Programmable Memory Array." FIG. 1 illustrates the layout of two columns of cells and their associated word lines, bit lines, power lines and fuses. As illustrated in FIG. 1, cell 2, indicated within the dashed line area, forms a first programmable cell comprising a compound semiconductor device and adjacent to cell 2 is illustrated, cell 3, indicated within dashed line 3. The cells in fuse programmable array 1 are served by bit lines, word lines, and power lines, and more particularly with respect to cell 2, bit line 4 which is connected to source region 5 via fuse 6. Word line 7 is connected to gate 8 of cell 2 and power line 9 is connected to drain region 10. As is well known to those skilled in the art, cell 2 is programmed by opening fuse 6 to sever the connection between bit line 4 and source region 5 or in the alternative, retaining the connection between bit line 4 and source region 5. In similar fashion, cell 3 is served by an associated bit line 11 which is coupled to source region 12 via programmable fuse 13. Also, cell 3 includes gate 13 which is connected to said word line 7, and drain region 14 which is connected to power line 15. In a typical prior art array such as that illustrated in FIG. 1, a conservative approach was taken in the layout to provide sufficient room around the fusable links, such as 6 and 13, to enable the easy programming of said links by laser beam application. As will be noted by reference to FIG. 1, there is wasted space around each fusable link since the area required for the cells is partially determined by the width of the FET in the cell. This provides more space around each link than is necessary for laser beam considerations. Thus it is desirable to provide a more sense array design to permit the production of arrays having more cells per unit area. As noted above, it will be appreciated that a substantial amount of unused substrate area is found around each fusible link, which area could better be used for the inclusion of additional cells.